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Elsevier

AI-Driven Optimization and Automation of Integrated Circuit Design

  • 1 Edición - 1 de octubre de 2026
  • Última edición
  • Editores: Neha Singh, Shilpi Birla, Chetan Arvind Patil
  • Idioma: Inglés

AI-Driven Optimization and Automation of Integrated Circuit Design discusses the latest AI-based methods, algorithms, architectures, and frameworks for digital, analog, and mixed-… Leer más

Descripción

AI-Driven Optimization and Automation of Integrated Circuit Design discusses the latest AI-based methods, algorithms, architectures, and frameworks for digital, analog, and mixed-signal VLSI circuit design, verification and testability, physical design and related areas. The book considers the issues with traditional circuit design and explains how machine learning techniques can optimize and automate the process. It goes on to explain how AI-driven design can impact logic synthesis, circuit placement and routing, and behavioral simulation. Final sections include cases studies and a look at future developments for implementations of VLSI design, IC design, and hardware realization using AI tools and techniques.

Artificial Intelligence (AI) offers a solution to the bottleneck issues in the design of integrated circuits (IC) by optimizing and automating tasks in the design and fabrication process. As the world focuses on the development of skilled manpower and automation tools for chip design, verification, testing and fabrication, AI can be utilized to optimize and automate various steps in design cycle, saving time, reducing errors, and managing power consumption.

Puntos claves

  • Explains how AI algorithms can significantly speed up the IC design process by automating tasks
  • Describes how AI can enhance precision in circuit design by reducing errors and improving design verification through predictive analysis
  • Offers insights into how to integrate AI tools and techniques into existing EDA (Electronic Design Automation) workflows

De interès para

Researchers in the field of VLSI design, computer engineering, electronics and automation for silicon design and development.

Índice

1. Automation in Analog Circuit Design using AI

2. Neural Network for Logic Synthesis Optimization

3. Machine Learning Approaches to Fault Detection in Circuit Design

4. Enhancing Chip Verification using AI

5. AI Applications in Digital Design for Testability (DFT

6. Machine leaning based power estimation in VLSI Design

7. Next-Gen IC Fault Detection using Advanced Machine Learning Algorithms – A Comprehensive Survey

8. AI-driven high level synthesis and behavioral simulation in VLSI design

9. Leveraging machine learning algorithms for designing analog and RF integrated circuits

10. Challenges with traditional integrated circuits design methods

11. Optimization techniques in ML for VLSI design

Detalles del producto

  • Edición: 1
  • Última edición
  • Publicado: 1 de octubre de 2026
  • Idioma: Inglés

Sobre los editores

NS

Neha Singh

Dr Neha Singh is a well-rounded and dynamic teaching professional with 20+ years of in-depth experience in educating undergraduate and postgraduate engineering students in Electronics & Communication Engineering. She is currently working as Assistant Professor, in the Department of Electronics & Communication Engineering at Manipal University Jaipur, Rajasthan, India. She did her PhD in the year 2020. Her areas of research interest include Image Processing, Machine learning, VLSI design and nanodevices. She has several papers and book chapters published in Journals, books and conferences of repute. She has co-authored engineering textbooks and edited three Scopus indexed books on Nanotechnology, Low power circuit design and predictive analytics with CRTC Press and IEEE-Wiley. She has served as reviewer in various International and peer reviewed Journals and conferences and delivered talks at national and international level events. She has also worked as Convener, Session Chair and organizer of various international conferences, summer internships including summer course on Diode Fabrication and Faculty Development Program in the domain of image processing as well as VLSI Testing. She has guided several M Tech Dissertations and B Tech projects and guiding PhD scholars as well. She is a Senior Member of IEEE.

Afiliaciones y experiencia
Assistant Professor, Electronics and Communication Engineering, Manipal University Jaipur, India

SB

Shilpi Birla

Dr Shilpi Birla is working as a Professor in Electronics & Communication Department at Manipal University Jaipur. She has a teaching and industrial experience of more than 15 years. She did her Ph D in Low Power VLSI Design. Her research interests are Low Power VLSI Design, Memory Circuits, Digital VLSI Circuits, Nanodevices and Image Processing. She has authored more than 60 research papers in journals of repute and International conferences. She has organized several workshops in HSPICE, TCAD and XILINX, Summer internships in Diode Fabrication and Faculty Development Programs. She has worked as a session chair, conference steering committee member, editorial board member, and reviewer in international/national IEEE Journal and conferences. She has guided many M. Tech Students and guiding Ph.D. students. She is a senior member of IEEE.

Afiliaciones y experiencia
Associate Professor, Electronics and Communication Department, Manipal University Jaipur, India

CP

Chetan Arvind Patil

Mr. Chetan Arvind Patil is a Principal Engineer at Marvell Semiconductor Inc., USA, with over 10+ years of experience in the semiconductor industry. He focuses on Test Engineering and Customer Strategy for AI custom ASICs, driving scalable test methodologies, yield optimization, and manufacturing readiness for advanced compute silicon. He is actively engaged in global semiconductor initiatives spanning standards, industry forums, and roadmap development. He contributes to various IEEE initiatives, including IEEE Global Semiconductors (an Ad Hoc of the IEEE Future Directions Committee), supporting technical discussions on AI-driven semiconductor development, manufacturing scalability, and ecosystem evolution. He is actively involved in IEEE Standards activities, serves on the IEEE Senior Member Application Panel, and contributes as a committee member and reviewer for multiple IEEE conferences. He has also contributed to the Heterogeneous Integration Roadmap under the IEEE Electronics Packaging Society (EPS) and delivered 15+ invited talks at global universities and industry forums, and has supported the MAPT Roadmap under the Semiconductor Research Corporation. Chetan is the author of 30+ semiconductor-focused articles covering yield, testing, chiplets, reliability, and manufacturing trends, published in international industry media. He also maintains a semiconductor blog, www.ChetanPatil.in, with 300+ articles aimed at knowledge sharing across the ecosystem. He holds dual Master of Science degrees in Computer Engineering from Arizona State University and Northwestern University, and a Bachelor of Engineering in Electronics and Telecommunication from Pune Institute of Computer Technology, India. He is a Senior Member of IEEE.

Afiliaciones y experiencia
Principal Engineer - Test Engineering, Marvell Semiconductor, USA